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Reducing test time using regression algorithms in post silicon validation
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| dc.contributor.author | Mamodia, Shivani | |
| dc.contributor.author | Subramanyam, A V (Advisor) | |
| dc.date.accessioned | 2024-06-13T12:06:04Z | |
| dc.date.available | 2024-06-13T12:06:04Z | |
| dc.date.issued | 2020-07-01 | |
| dc.identifier.uri | http://repository.iiitd.edu.in/xmlui/handle/123456789/1638 | |
| dc.language.iso | en_US | en_US |
| dc.publisher | IIIT-Delhi | en_US |
| dc.title | Reducing test time using regression algorithms in post silicon validation | en_US |
| dc.type | Thesis | en_US |
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Year-2020 [13]