Abstract:
Embedded memories occupy up to 70% of the area and account for 30-50% power consumption in advanced digital SoCs. A large part of this power is leakage power. Therefore, high-density, low-leakage SRAM cells are desirable. We propose two asymmetrical SRAM cells and benchmark with conventional 6T, 5T, and 4T SRAM cells. The first SRAM cell is a 4TA asymmetrical SRAM cell. We designed it under isostable constraints. We show that in a 130nm CMOS technology, the proposed 4TA cell is denser by up to 7% than 6T SRAM cells and has about 4X lower leakage than 6T SRAM cells. However, the performance is lower in 4TA as compared to 6T SRAM. The second SRAM is a 5TA asymmetrical SRAM cell. We designed 5TA under isoarea constraints. Our analysis shows that the proposed 5TA cell has about 10X and 6.23X lower leakage than the conventional SRAM cell in 130nm and 65nm CMOS technology, respectively at a similar performance point.
