Abstract:
As CMOS technology continues to scale, integrated circuits are increasingly susceptible to radiation-induced disruptions, necessitating resilient yet efficient hardening techniques. Conventional radiation-hardened flip-flops often incur significant penalties in power, area, and performance, while overlooking sustainability concerns. This thesis proposes a novel radiation- hardened flip-flop architecture that enhances robustness against transient and upset events by employing a master-slave configuration with comprehensively protected storage nodes and con- trolled delay elements. The design is optimized to reduce both area and power overheads while effectively mitigating fault propagation. Additionally, we introduce a unified Power, Performance, Area, and Sustainability (PPAS) evaluation framework that holistically assesses circuit efficiency, incorporating both embodied and operational energy components to quantify environmental impact. Implemented in 65nm CMOS technology and validated using Cadence Virtuoso, the proposed flip-flop demonstrates enhanced resilience and improved energy-conscious performance compared to existing solutions. The comparative analysis highlights consistent advantages in area, power, and environmental sustainability. By embedding sustainability metrics into early-stage design evaluation, this work contributes to the advancement of dependable and eco-friendly integrated circuits suitable for radiation-exposed applications.
