Impact of “Flip-Flop” design choices on sustainability for HPC application

Abstract

As environmental concerns rise, the industry faces pressure to reduce energy consumption. Research has been going on to design energy-efficient designs, particularly in low-power, high-performance applications. Flip-flops are an integral component that is used in almost all digital circuits and analogue/Digital mixed systems, as they are very important for data storage and processing. As dynamic power mainly depends on activity factor and frequency, and accordingly, power dissipation can vary based on input data and clock. In this thesis, both single-edge triggered flip flops (SETFF) and dual-edge trigerred flip flops (DETFF) have been studied. To achieve the same data throughput as in a single-edge triggered flip-flop, a dual-edge triggered flip-flop is an optimum way to reduce power dissipation. In this thesis, SETFF and DETFF designs are evaluated for both Iot and HPC applications. This thesis also proposes a novel Sustainability Framework to allow designers to assess, benchmark, and choose the most efficient and environment-friendly architecture for their product development at the early design phase (i.e., schematic and layout). At the System-on-Chip (Soc) level, flip-flops make a significant contribution due to their widespread use across various intellectual property (IP) blocks. Therefore, analysing these flip-flops for their role in greener circuit designs is crucial, as it plays a key part in advancing sustainable design practices. The overall analysis shows that the operational footprint is far more important than the embodied footprint for HPC applications.