Abstract:
Recent advancements in the semiconductor industry have paved the way for a broader use of semiconductor chips in various areas such as computing, data processing, and communication. Adders, which are the smallest and most common building blocks in these applications, play a critical role. With the exponential growth in data, there is a significant increase in power demand, leading to a rising interest in approximate adders. These adders are particularly effective in saving power for error-resilient applications like image and video processing, as well as data computation. As the utilization of semiconductor chips continues to expand, the traditional evaluation framework that focuses on Power, Performance, and Area (PPA) is no longer adequate for assessing the environmental impact of these designs. Consequently, there is a need for a new approach that evaluates designs based on Power, Performance, Area, and Sustainability (PPAS). This sustainability evaluation paradigm broadens the analysis to include the environmental effects of both fabrication and operation, ensuring long-term efficiency and a reduced carbon footprint. In this study, a set of approximate adder architectures has been benchmarked using a novel sustainability-focused evaluation framework in 65-nm low standby power technology. This benchmarking approach allows designers to choose the most efficient and sustainable approximate adder architecture from the available options.
