Impact of level shifter design choices on sustainability

Abstract

In this advancing era of technology and innovation, semiconductor development has exploded, enabling researchers to develop cutting-edge, ultra-low-power, and high-speed integrated circuits. However, this scaling progress in semiconductors is having a detrimental impact on the environment by overexploiting its available resources. Hence, to mitigate this impact, the VLSI industry is shifting its focus toward environmentally sustainable IC manufacturing, moving beyond the traditional Power, Performance, and Area (PPA) approach. Currently, most proposed sustainability evaluation approaches operate at higher abstraction levels, such as the SoC/product level, rather than at the individual logic cell level. In this work, we address this requirement by proposing a novel sustainability evaluation paradigm and validating it on different Level Shifter cell architectures. A Level Shifter is a low-power design technique used to facilitate data communication between multi-voltage domains in an SoC. Along with the proposed paradigm, we also introduce a unique double-row layout design technique for Level Shifters to enhance area optimization and analyze its impact on sustainability.