Abstract:
Analog-to-Digital Converters (ADCs) are essential components bridging analog inputs with digital processing systems. Among various architectures, Successive Approximation Register (SAR) ADCs are known for their power and area efficiency but are inherently limited in speed due to their sequential bit-by-bit operation. To overcome this, we implemented and compared two ADC architectures: a conventional SAR ADC and a pipelined SAR ADC, both fabricated in 65nm CMOS technology. The pipelined architecture splits the conversion into two 4-bit stages, allowing it to operate at half the clock frequency while achieving the same throughput as the SAR ADC. Although the SAR ADC occupies about 70% of the area of the pipelined SAR ADC, the pipelined design delivers significantly better performance while maintaining reasonable area and power trade-offs. Additionally, sustainability analysis reveals that the pipelined SAR ADC achieves an approximately 11% lower total carbon footprint compared to the conventional SAR ADC, highlighting the impact of architectural optimization on both performance and environmental metrics. These results underscore that strategic architectural improvements can lead to substantial gains in both system performance and sustainability.
