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Now showing items 1-10 of 36

High efficiency fully integrated PLL based low-dropout voltage regulator

Singh, Ankush; Hashmi, Mohammad S. (Advisor) (2017-06)
Identification of weak bits in SRAM

Kumar, Gundu Anil; Hashmi, Mohammad S. (Advisor) (2015-12-07)
Predictive analysis of safety subsystems in memories for diagnostic coverage

Srinivasan, Arvind; Hashmi, Mohammad S. (Advisor); Janardan, Dhori Kedar (Advisor) (2015-12-07)
Mitigation of cold boot attack using an encrypted memory controller

Walia, Preet Kaur; Hashmi, Mohammad S. (Advisor) (2016-09-12)
Time to digital converter for all digital PLL in 65 nm CMOS technology

Shukla, Vipra; Hashmi, Mohammad S. (Advisor) (2017-07-09)
Designing dual band impedance matching transformer.

Singh, Vikas Vikram; Hashmi, Mohammad S. (Advisor) (IIIT-Delhi, 2018-04-18)
Analytical formulations for systematic design of dual-/tri-frequency impedance transformation networks required in software-defined radios (SDRs) and energy harvesting applications

Maktoomi, Md Ayatullah; Hashmi, Mohammad S. (Advisor) (2016-10-14)
Process, voltage and temperature compensated oscillator for phase change memories

Tyagi, Vivek; Hashmi, Mohammad S. (Advisor) (2017)
Multiple valued current mode logic circuits

Tarun, Kunwar; Hashmi, Mohammad S. (Advisor) (2017-05)
Exploration of test methodologies to detect weak bits in SRAMs

Batra, Nidhi; Hashmi, Mohammad S. (Advisor) (2016-09-12)

Now showing items 1-10 of 36