IIIT-Delhi Institutional Repository

Browsing MTech Theses by Issue Date

Browsing MTech Theses by Issue Date

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  • Dynamic memory management for resource contrained next generation wireless sensor nodes 
    Das, Supratim; Singh, Amarjeet (Advisor) (2014-07-10)
    Wireless Sensor Nodes are very low power resource constrained devices with limited radio communications ability. As the technology is evolving at a rapid pace, more and more complex protocols and applications are integrated ...
  • Realistic rendering of 3D avatar using physics simulation and minimal sensors 
    Acharya B, Srikrishna; Sujit, PB (Advisor) (2014-07-10)
    Physics simulation o ers the option of truly receptive and realistic animation. Although wide ac- ceptance of physics simulation for the animation, commercial applications still relies on kinematics- based approaches for ...
  • Reliability aware intelligent memory management (RAIMM) 
    Rout, Sidhartha Sankar; Deb, Sujay (Advisor) (2014-07-10)
    The growing technology scaling and larger die size of multi-processor System-on-Chip (SoC) have increased the error rates for on-chip memories. Increased system speed for high performance, aggressive voltage scaling for ...
  • Two dimensional metamaterial slot antenna for improved directivity 
    Jain, Rohit; Ram, Shobha Sundar (Advisor) (2014-07-10)
    Directivity of an antenna is a figure of merit which shows how effective an antenna is at transmitting / receiving in a desired direction. A highly directive antenna is useful for applications such as satellite communications ...
  • UVM based STBUS veri cation IP for verifying SoC 
    Samanta, Pranay; Deb, Sujay (Advisor) (2014-07-10)
    The ever increasing advances in the integrated circuit technology made it possible for electronic system designers to assemble complete systems-on-chips (SoC). As these SoCs have been used in computer, graphics, and ...
  • Signal processing techniques to reduce energy consumption in EEG acquisition and transmission for WBAN 
    Shukla, Ankita; Srinivasan, Ashwin (Advisor) (2014-07-10)
    Recently there has been a lot of interest in health tele-monitoring. Some vital heath indicators like EEC, ECG, MEG, Pulse Plethysmograph etc. are collected by sensor nodes; the acquired signal is transmitted to a remote ...
  • A wordline voltage management for NOR type flash memories 
    Sinha, Rohan; Hashmi, Mohammad S. (Advisor) (2014-07-11)
    Today, in every electronic system, some information must be stored even when the system is not powered. Solid state non-volatile memories are used for storing those information which should not be lost even when the power ...
  • A generic technique to develop human tissue phantom 
    Rahman, Mir Mohsina; Hashmi, Mohammad S. (Advisor) (2014-07-11)
    Recent trends show increasing cases of implantable devices for monitoring and control of organs such as heart. The implantation of devices requires a multi stage evaluation process in order to make sure that these devices ...
  • Design of energy e cient future CMPs with on-chip wireless interconnects 
    Sri Harsha, Gade Narayana; Srinivasan, Ashwin (Advisor) (2014-07-17)
    Power density and interconnect delay have emerged as the biggest challenges for Ultra Large Scale Integration (ULSI) and System-on-Chip (SoC) designs particularly beyond 65nm generation. Leakage power has been traditionally ...
  • Study, analysis and modeling of electromigration in SRAMs 
    Kumar, Neeraj; Hashmi, Mohammad S. (Advisor) (IIIT Delhi, 2014-09-05)
    Today, the VLSI industry is matching the pace with the Moore‟s law which states that in every 18 months the number of transistors on integrated chip would get doubled. This essentially means that with the advancement of ...
  • Fixed-point digital predistortion system for nonlinear high power amplifiers 
    Dwivedi, Namrata; Bohara, Vivek Ashok (Advisor) (IIIT Delhi, 2014-09-05)
    Radio Frequency (RF) High Power Amplifiers (HPAs) are one of the basic building blocks of modern wireless communication system. But most of these broadband wireless communication systems such as Universal Mobile ...
  • Analysis and estimation of jitter sub-components 
    Sharma, Vijender Kumar; Deb, Sujay (Advisor) (IIIT Delhi, 2014-09-06)
    Maintaining quality of signal transmission is a major challenge with the increasing speed of data transmission in Nano-scale VLSI technology. The decreasing voltage margins at the same time, makes it even stringent to ...
  • Improvement in static timing analysis for early ta-signoff closure in soc flow at very deep submicron nodes 
    Singh, Vinod Kumar; Biswas, R. N. (Advisor) (IIIT Delhi, 2014-09-06)
    An approach is proposed to improve static timing analysis for early TA-signoff closure at Very Deep Sub-Micron (V-DSM) nodes. At higher technology nodes (>100nm) the timing path delay is governed mainly by the cells, and ...
  • Executable model based design methodology for fast prototyping of mobile network protocol : a case study on mipi lli 
    Shah, Rahul Kumar; Fell, Alexander (Advisor) (IIIT Delhi, 2014-09-06)
    Future mobile communication systems incorporate more sophisticated functionalities which im- prove their performance and increase their complexity. In order to reduce their time to market, the RTL development as well the ...
  • Mobile hotspot selection and offloading 
    Mittal, Vandana; Kaul, Sanjit Krishnan (Advisor) (2015-09-28)
    The adoption of smartphones, their ability to configure as mobile hotspots (WiFi access points), together with access to cellular networks, creates novel possibilities of heterogeneous network access for users. Specifically, ...
  • Methodological framework for automation of hardware software co-validation of an IP 
    Jain, Abhinav; Fell, Alexander (Advisor) (2015-12-05)
    The VLSI industry is witnessing rapid changes driven by the growing mar- ket requirements. In order to maintain their competitive quotient, reducing the time to market of their IC products has become a prime concern of ...
  • Smart and efficient multi-scenario SoC timing closure and ECO generator 
    Sharma, Aditi; Deb, Sujay (Advisor) (2015-12-05)
    Signoff timing analysis is still considered as a critical element in the SoC design flow. With the advancements of the leading edge technologies towards the deep sub-micron realms, the performance of a multi-million ...
  • Razor flop based on chip delay measurement 
    Vasisth, Aditya; Hashmi, Mohammad S. (Advisor); Jain, Abhishek (Advisor) (2015-12-05)
    Moving towards deep submicron technologies, consideration for design margin will increase. In these technologies, process variation will increase the requirements of design margins. Lower supply voltage and higher clock ...
  • Predictive analysis of safety subsystems in memories for diagnostic coverage 
    Srinivasan, Arvind; Hashmi, Mohammad S. (Advisor); Janardan, Dhori Kedar (Advisor) (2015-12-07)
    Automobile safety is becoming an important subject because of the large number of electronic systems being integrated within a System on Chip (SoC) and with the use of current state-of-the-art technology, safety is becoming ...
  • Floorplan aware framework for optimal SRAM selection for memory subsystems 
    Narang, Gaurav; Fell, Alexander (Advisor) (2015-12-07)
    Embedded memories are the key contributor to the chip area, dynamic power dissipation and also form a signicant part of critical path for high performance advanced SoCs. Therefore, optimal selection of memory instances ...

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